Waymo has disclosed the custom silicon and system architecture behind its latest robotaxi compute, offering platform teams a rare production view of low-latency AI at the edge.
NEW DELHI, Aug. 23, 2026, 6:07 p.m. IST — Waymo has revealed a purpose-built 5-nanometre AI processor and the redundant onboard computer that runs its latest autonomous vehicles, showing how the Alphabet company is moving critical perception workloads closer to sensors while retaining a mix of CPUs, GPUs and other accelerators.
The disclosure matters beyond autonomous driving. It is a production case study in operating AI where a cloud retry is not an option: inference must finish within milliseconds, hardware has to survive vibration and extreme temperatures, and a single compute failure cannot be allowed to stop the system. For developers and platform engineers building robotics, industrial inspection or other edge-AI services, Waymo’s design highlights why latency budgets, failure isolation and achieved performance can matter more than a headline model benchmark.
What Waymo confirmed
In a technical post published ahead of the Hot Chips 2026 conference, Waymo said its latest system uses a custom 5 nm application-specific integrated circuit to process raw camera, lidar and radar data and run neural networks in real time. The company described the ASIC as a front-end processor for tasks including sensor fusion and temporal denoising in low-light conditions.
Waymo said the ASIC layer delivers more than 1,000 trillion operations per second of machine-learning performance. That is a vendor-reported theoretical throughput figure, not an independently reproduced measure of end-to-end driving performance. The company did not publish power draw, die size, memory capacity, manufacturing yield or a direct cost comparison with an off-the-shelf design.
The latest platform processes feeds from 13 high-resolution cameras simultaneously, according to Waymo. Its onboard compute has grown by 20 times over eight years, while software and hardware are co-designed to reduce the delay from the first captured pixel to a vehicle action. Waymo said the architecture runs advanced models ranging from sparse convolutions to dense transformers, with special attention to the low-batch inference patterns typical of a moving vehicle.
A heterogeneous system, not one magic chip
The custom ASIC is only one part of the vehicle computer. Waymo pairs its machine-learning accelerators with CPUs, GPUs and other components for orchestration, data movement, logging and workloads that do not fit the custom silicon. It named AMD, Micron, Nvidia, Samsung, Sandisk, Socionext and TSMC among its technology partners.
That distinction is important. Reuters reported that the move reduces Waymo’s exclusive dependence on third-party accelerators, but Nvidia remains in the supplier set. The available evidence therefore points to selective specialization inside a heterogeneous platform, not a wholesale replacement of general-purpose compute.
The system is also designed as two independent compute engines. Both normally run full parallel workloads, but Waymo says either can take over after a fault. The hardware connects to the vehicle’s liquid-cooling system so it can sustain performance through hot and cold operating conditions without adding cabin noise or consuming excessive interior space.
Waymo’s Hot Chips schedule supports the timing and scope of the disclosure. Compute lead Daniel Rosenband is due to give a keynote on autonomous-driving compute on Aug. 24, followed by a separate presentation on the company’s sensor-fusion processor. More detailed specifications may emerge from those sessions, so some architectural and efficiency questions remain open at publication time.
What platform teams can take from the design
The first lesson is to design from a service-level objective back to the hardware. Waymo optimises the full path from sensor input to actuation rather than treating peak TOPS as the product. Teams deploying edge inference should measure tail latency, queueing, memory movement, thermal throttling and deadline misses under representative inputs, not only average tokens or frames per second in a lab.
The second is to separate the real-time data plane from supporting work. Sensor preprocessing and fusion sit on specialised accelerators, while orchestration, logging and other tasks run elsewhere. A similar boundary can prevent observability exports, model downloads or background maintenance from stealing resources from a safety- or revenue-critical inference path.
The third is to make failover a system property. Running two engines is expensive, but the architecture illustrates a broader principle: redundancy only helps when state, health checks and handoff behaviour are tested together. Platform teams should inject accelerator, sensor, memory and thermal faults and verify that degraded operation remains within a defined envelope. This is the physical-AI equivalent of testing a multi-zone service rather than assuming a second replica is enough.
Finally, co-design increases both efficiency and release-management burden. A model update that changes precision, sparsity, memory access or operator support can invalidate hardware assumptions. Treating models, kernels, firmware, calibration data and safety policies as one versioned release unit can reduce configuration drift. Teams beginning that work may also find GravityDevOps’ guides to LLMOps and CI/CD tool selection useful for adapting familiar controls to AI artefacts.
Balanced reading of the announcement
Waymo’s disclosure is significant because it exposes concrete production constraints, but it does not by itself prove safer driving, lower fleet cost or superiority over another autonomous-vehicle stack. The company linked its architecture to more than 200 million fully autonomous miles, while its public post did not provide a controlled before-and-after comparison connecting the new ASIC to a specific safety outcome.
Independent reporting provides useful scale context. TechCrunch reported in May that Waymo’s sixth-generation Ojai vehicle uses 13 cameras, four lidar units and six radar sensors, and that Waymo was serving more than 500,000 paid rides per week. Those operating figures show why hardware efficiency and repeatable deployment matter, but they should not be read as validation of the new chip’s performance claims.
The clearest conclusion for engineering teams is narrower: mature AI products increasingly depend on the system around the model. In Waymo’s case, that system includes custom sensor processing, heterogeneous compute, cooling, redundancy, logging and a release process that has to work on thousands of moving edge nodes. The architecture is a reminder that production AI reliability is built across the whole path, not purchased as a single accelerator specification.
Sources
Waymo’s onboard compute disclosure; the official Hot Chips 2026 programme; TechCrunch’s report on Waymo’s sixth-generation Ojai vehicle; and Reuters reporting on the custom chip.
